/***********************************************************************\
*                                                                       *
* This file was created by Component Internal Interface Engine software *
*  Copyright(c) 2000-2012 by Krzysztof Pozniak (pozniak@ise.pw.edu.pl)  *
*                           All Rights Reserved.                        *
*                                                                       *
\***********************************************************************/

package cii_kx1_car3;

import cii_lib.*;

public class CCII_DPM_DDR {

  public CCII_COMPONENT _CII_DPM_DDR;

  private CCII_ACCESS_IPAR _IPAR_DATA_WIDTH;
  private CCII_ACCESS_IPAR _IPAR_BUF_ADDR_WIDTH;
  private CCII_ACCESS_IPAR _IPAR_DDR_ADDR_WIDTH;
  private CCII_ACCESS_IPAR _IPAR_DDR_MASK_WIDTH;
  private CCII_ACCESS_IPAR _IPAR_DDR_ADDR_SHIFT;
  private CCII_ACCESS_HPAR _HPAR_DDR_ADDR_SWAP;
  private CCII_ACCESS_IPAR _IPAR_DDR_BASE_WIDTH;
  private CCII_ACCESS_IPAR _IPAR_BUF_READ_LATENCY;
  public class CMPAR_PROC_RUN_CII extends CCII_ACCESS_MPAR {
    public CMPAR_PROC_RUN_CII(CCII_TABLE_INDEX itab, CCII_COMPONENT comp) { super(itab,comp);}
    public CCIISYS.CLIST_INTERF_CTRL GetList() {return(CCIISYS.LIST_INTERF_CTRL);}
  };
  private CMPAR_PROC_RUN_CII _MPAR_PROC_RUN_CII;
  private CCII_ACCESS_LPAR _LPAR_PROC_ACTIVE_CII;
  private CCII_ACCESS_LPAR _LPAR_PROC_ERROR_CII;
  private CCII_ACCESS_LPAR _LPAR_DPM_TRAN_READY_CII;
  public class CMPAR_DPM_TRAN_ACK_CII extends CCII_ACCESS_MPAR {
    public CMPAR_DPM_TRAN_ACK_CII(CCII_TABLE_INDEX itab, CCII_COMPONENT comp) { super(itab,comp);}
    public CCIISYS.CLIST_INTERF_CTRL GetList() {return(CCIISYS.LIST_INTERF_CTRL);}
  };
  private CMPAR_DPM_TRAN_ACK_CII _MPAR_DPM_TRAN_ACK_CII;
  public class CMPAR_DDR_TRAN_AUTO_CII extends CCII_ACCESS_MPAR {
    public CMPAR_DDR_TRAN_AUTO_CII(CCII_TABLE_INDEX itab, CCII_COMPONENT comp) { super(itab,comp);}
    public CCIISYS.CLIST_INTERF_CTRL GetList() {return(CCIISYS.LIST_INTERF_CTRL);}
  };
  private CMPAR_DDR_TRAN_AUTO_CII _MPAR_DDR_TRAN_AUTO_CII;
  public class CMPAR_DDR_TRAN_SIM_CII extends CCII_ACCESS_MPAR {
    public CMPAR_DDR_TRAN_SIM_CII(CCII_TABLE_INDEX itab, CCII_COMPONENT comp) { super(itab,comp);}
    public CCIISYS.CLIST_INTERF_CTRL GetList() {return(CCIISYS.LIST_INTERF_CTRL);}
  };
  private CMPAR_DDR_TRAN_SIM_CII _MPAR_DDR_TRAN_SIM_CII;
  public class CMPAR_DDR_ADDR_CII extends CCII_ACCESS_MPAR {
    public CMPAR_DDR_ADDR_CII(CCII_TABLE_INDEX itab, CCII_COMPONENT comp) { super(itab,comp);}
    public CCIISYS.CLIST_INTERF_CTRL GetList() {return(CCIISYS.LIST_INTERF_CTRL);}
  };
  private CMPAR_DDR_ADDR_CII _MPAR_DDR_ADDR_CII;
  public class CMPAR_DDR_MASK_CII extends CCII_ACCESS_MPAR {
    public CMPAR_DDR_MASK_CII(CCII_TABLE_INDEX itab, CCII_COMPONENT comp) { super(itab,comp);}
    public CCIISYS.CLIST_INTERF_CTRL GetList() {return(CCIISYS.LIST_INTERF_CTRL);}
  };
  private CMPAR_DDR_MASK_CII _MPAR_DDR_MASK_CII;
  public class CMPAR_DDR_NUM_CII extends CCII_ACCESS_MPAR {
    public CMPAR_DDR_NUM_CII(CCII_TABLE_INDEX itab, CCII_COMPONENT comp) { super(itab,comp);}
    public CCIISYS.CLIST_INTERF_CTRL GetList() {return(CCIISYS.LIST_INTERF_CTRL);}
  };
  private CMPAR_DDR_NUM_CII _MPAR_DDR_NUM_CII;
  public class CMPAR_DDR_WR0_RD1_CII extends CCII_ACCESS_MPAR {
    public CMPAR_DDR_WR0_RD1_CII(CCII_TABLE_INDEX itab, CCII_COMPONENT comp) { super(itab,comp);}
    public CCIISYS.CLIST_INTERF_CTRL GetList() {return(CCIISYS.LIST_INTERF_CTRL);}
  };
  private CMPAR_DDR_WR0_RD1_CII _MPAR_DDR_WR0_RD1_CII;
  public class CMPAR_DDR_TRAN_RUN_CII extends CCII_ACCESS_MPAR {
    public CMPAR_DDR_TRAN_RUN_CII(CCII_TABLE_INDEX itab, CCII_COMPONENT comp) { super(itab,comp);}
    public CCIISYS.CLIST_INTERF_CTRL GetList() {return(CCIISYS.LIST_INTERF_CTRL);}
  };
  private CMPAR_DDR_TRAN_RUN_CII _MPAR_DDR_TRAN_RUN_CII;
  private CCII_ACCESS_LPAR _LPAR_DDR_TRAN_STOP_CII;
  private CCII_ACCESS_LPAR _LPAR_MEM_ACC_CII;
  private CCII_ACCESS_IR _BITS_PROC_RUN;
  private CCII_ACCESS_RO _BITS_PROC_ACTIVE;
  private CCII_ACCESS_RO _BITS_PROC_ERROR;
  private CCII_ACCESS_RO _BITS_DPM_TRAN_READY;
  private CCII_ACCESS_IR _BITS_DPM_TRAN_ACK;
  private CCII_ACCESS_IR _BITS_DDR_TRAN_AUTO;
  private CCII_ACCESS_IR _BITS_DDR_TRAN_SIM;
  private CCII_ACCESS_IR _BITS_DDR_WR0_RD1;
  private CCII_ACCESS_IR _BITS_DDR_TRAN_RUN;
  private CCII_ACCESS_RO _BITS_DDR_TRAN_STOP;
  private CCII_ACCESS_IR _WORD_DDR_ADDR;
  private CCII_ACCESS_IR _WORD_DDR_MASK;
  private CCII_ACCESS_IR _WORD_DDR_NUM;
  private CCII_DPM[] _COMP_DPM;
  public CCII_DPM_DDR(CCII_TABLE_INDEX itab, int cidx, CCII_INTERFACE interf, CCII_COMPONENT parent) {
    _CII_DPM_DDR=new CCII_COMPONENT(itab,cidx,parent);
    _IPAR_DATA_WIDTH=null;
    _IPAR_BUF_ADDR_WIDTH=null;
    _IPAR_DDR_ADDR_WIDTH=null;
    _IPAR_DDR_MASK_WIDTH=null;
    _IPAR_DDR_ADDR_SHIFT=null;
    _HPAR_DDR_ADDR_SWAP=null;
    _IPAR_DDR_BASE_WIDTH=null;
    _IPAR_BUF_READ_LATENCY=null;
    _MPAR_PROC_RUN_CII=null;
    _LPAR_PROC_ACTIVE_CII=null;
    _LPAR_PROC_ERROR_CII=null;
    _LPAR_DPM_TRAN_READY_CII=null;
    _MPAR_DPM_TRAN_ACK_CII=null;
    _MPAR_DDR_TRAN_AUTO_CII=null;
    _MPAR_DDR_TRAN_SIM_CII=null;
    _MPAR_DDR_ADDR_CII=null;
    _MPAR_DDR_MASK_CII=null;
    _MPAR_DDR_NUM_CII=null;
    _MPAR_DDR_WR0_RD1_CII=null;
    _MPAR_DDR_TRAN_RUN_CII=null;
    _LPAR_DDR_TRAN_STOP_CII=null;
    _LPAR_MEM_ACC_CII=null;
    _BITS_PROC_RUN=null;
    _BITS_PROC_ACTIVE=null;
    _BITS_PROC_ERROR=null;
    _BITS_DPM_TRAN_READY=null;
    _BITS_DPM_TRAN_ACK=null;
    _BITS_DDR_TRAN_AUTO=null;
    _BITS_DDR_TRAN_SIM=null;
    _BITS_DDR_WR0_RD1=null;
    _BITS_DDR_TRAN_RUN=null;
    _BITS_DDR_TRAN_STOP=null;
    _WORD_DDR_ADDR=null;
    _WORD_DDR_MASK=null;
    _WORD_DDR_NUM=null;
    _COMP_DPM=null;
    int _cnum_;
    if(_CII_DPM_DDR.Number()==0) return;
    _IPAR_DATA_WIDTH = new CCII_ACCESS_IPAR(itab,_CII_DPM_DDR);
    _IPAR_BUF_ADDR_WIDTH = new CCII_ACCESS_IPAR(itab,_CII_DPM_DDR);
    _IPAR_DDR_ADDR_WIDTH = new CCII_ACCESS_IPAR(itab,_CII_DPM_DDR);
    _IPAR_DDR_MASK_WIDTH = new CCII_ACCESS_IPAR(itab,_CII_DPM_DDR);
    _IPAR_DDR_ADDR_SHIFT = new CCII_ACCESS_IPAR(itab,_CII_DPM_DDR);
    _HPAR_DDR_ADDR_SWAP = new CCII_ACCESS_HPAR(itab,_CII_DPM_DDR);
    _IPAR_DDR_BASE_WIDTH = new CCII_ACCESS_IPAR(itab,_CII_DPM_DDR);
    _IPAR_BUF_READ_LATENCY = new CCII_ACCESS_IPAR(itab,_CII_DPM_DDR);
    _MPAR_PROC_RUN_CII = new CMPAR_PROC_RUN_CII(itab,_CII_DPM_DDR);
    _LPAR_PROC_ACTIVE_CII = new CCII_ACCESS_LPAR(itab,_CII_DPM_DDR);
    _LPAR_PROC_ERROR_CII = new CCII_ACCESS_LPAR(itab,_CII_DPM_DDR);
    _LPAR_DPM_TRAN_READY_CII = new CCII_ACCESS_LPAR(itab,_CII_DPM_DDR);
    _MPAR_DPM_TRAN_ACK_CII = new CMPAR_DPM_TRAN_ACK_CII(itab,_CII_DPM_DDR);
    _MPAR_DDR_TRAN_AUTO_CII = new CMPAR_DDR_TRAN_AUTO_CII(itab,_CII_DPM_DDR);
    _MPAR_DDR_TRAN_SIM_CII = new CMPAR_DDR_TRAN_SIM_CII(itab,_CII_DPM_DDR);
    _MPAR_DDR_ADDR_CII = new CMPAR_DDR_ADDR_CII(itab,_CII_DPM_DDR);
    _MPAR_DDR_MASK_CII = new CMPAR_DDR_MASK_CII(itab,_CII_DPM_DDR);
    _MPAR_DDR_NUM_CII = new CMPAR_DDR_NUM_CII(itab,_CII_DPM_DDR);
    _MPAR_DDR_WR0_RD1_CII = new CMPAR_DDR_WR0_RD1_CII(itab,_CII_DPM_DDR);
    _MPAR_DDR_TRAN_RUN_CII = new CMPAR_DDR_TRAN_RUN_CII(itab,_CII_DPM_DDR);
    _LPAR_DDR_TRAN_STOP_CII = new CCII_ACCESS_LPAR(itab,_CII_DPM_DDR);
    _LPAR_MEM_ACC_CII = new CCII_ACCESS_LPAR(itab,_CII_DPM_DDR);
    _BITS_PROC_RUN = new CCII_ACCESS_IR(itab,interf,_CII_DPM_DDR);
    _BITS_PROC_ACTIVE = new CCII_ACCESS_RO(itab,interf,_CII_DPM_DDR);
    _BITS_PROC_ERROR = new CCII_ACCESS_RO(itab,interf,_CII_DPM_DDR);
    _BITS_DPM_TRAN_READY = new CCII_ACCESS_RO(itab,interf,_CII_DPM_DDR);
    _BITS_DPM_TRAN_ACK = new CCII_ACCESS_IR(itab,interf,_CII_DPM_DDR);
    _BITS_DDR_TRAN_AUTO = new CCII_ACCESS_IR(itab,interf,_CII_DPM_DDR);
    _BITS_DDR_TRAN_SIM = new CCII_ACCESS_IR(itab,interf,_CII_DPM_DDR);
    _BITS_DDR_WR0_RD1 = new CCII_ACCESS_IR(itab,interf,_CII_DPM_DDR);
    _BITS_DDR_TRAN_RUN = new CCII_ACCESS_IR(itab,interf,_CII_DPM_DDR);
    _BITS_DDR_TRAN_STOP = new CCII_ACCESS_RO(itab,interf,_CII_DPM_DDR);
    _WORD_DDR_ADDR = new CCII_ACCESS_IR(itab,interf,_CII_DPM_DDR);
    _WORD_DDR_MASK = new CCII_ACCESS_IR(itab,interf,_CII_DPM_DDR);
    _WORD_DDR_NUM = new CCII_ACCESS_IR(itab,interf,_CII_DPM_DDR);
    _COMP_DPM = new CCII_DPM[_cnum_=Math.max(itab.GetItem().Repeat,1)];
    for (int count=0; count<_cnum_; count ++)
      _COMP_DPM[count]=new CCII_DPM(itab,count,interf,_CII_DPM_DDR);
  }
  public CCII_COMPONENT CII_DPM_DDR() {return(_CII_DPM_DDR.Number()==0?null:_CII_DPM_DDR);};
  public CCII_ACCESS_IPAR IPAR_DATA_WIDTH() {return(_IPAR_DATA_WIDTH);};
  public CCII_ACCESS_IPAR IPAR_BUF_ADDR_WIDTH() {return(_IPAR_BUF_ADDR_WIDTH);};
  public CCII_ACCESS_IPAR IPAR_DDR_ADDR_WIDTH() {return(_IPAR_DDR_ADDR_WIDTH);};
  public CCII_ACCESS_IPAR IPAR_DDR_MASK_WIDTH() {return(_IPAR_DDR_MASK_WIDTH);};
  public CCII_ACCESS_IPAR IPAR_DDR_ADDR_SHIFT() {return(_IPAR_DDR_ADDR_SHIFT);};
  public CCII_ACCESS_HPAR HPAR_DDR_ADDR_SWAP() {return(_HPAR_DDR_ADDR_SWAP);};
  public CCII_ACCESS_IPAR IPAR_DDR_BASE_WIDTH() {return(_IPAR_DDR_BASE_WIDTH);};
  public CCII_ACCESS_IPAR IPAR_BUF_READ_LATENCY() {return(_IPAR_BUF_READ_LATENCY);};
  public CMPAR_PROC_RUN_CII MPAR_PROC_RUN_CII() {return(_MPAR_PROC_RUN_CII);};
  public CCII_ACCESS_LPAR LPAR_PROC_ACTIVE_CII() {return(_LPAR_PROC_ACTIVE_CII);};
  public CCII_ACCESS_LPAR LPAR_PROC_ERROR_CII() {return(_LPAR_PROC_ERROR_CII);};
  public CCII_ACCESS_LPAR LPAR_DPM_TRAN_READY_CII() {return(_LPAR_DPM_TRAN_READY_CII);};
  public CMPAR_DPM_TRAN_ACK_CII MPAR_DPM_TRAN_ACK_CII() {return(_MPAR_DPM_TRAN_ACK_CII);};
  public CMPAR_DDR_TRAN_AUTO_CII MPAR_DDR_TRAN_AUTO_CII() {return(_MPAR_DDR_TRAN_AUTO_CII);};
  public CMPAR_DDR_TRAN_SIM_CII MPAR_DDR_TRAN_SIM_CII() {return(_MPAR_DDR_TRAN_SIM_CII);};
  public CMPAR_DDR_ADDR_CII MPAR_DDR_ADDR_CII() {return(_MPAR_DDR_ADDR_CII);};
  public CMPAR_DDR_MASK_CII MPAR_DDR_MASK_CII() {return(_MPAR_DDR_MASK_CII);};
  public CMPAR_DDR_NUM_CII MPAR_DDR_NUM_CII() {return(_MPAR_DDR_NUM_CII);};
  public CMPAR_DDR_WR0_RD1_CII MPAR_DDR_WR0_RD1_CII() {return(_MPAR_DDR_WR0_RD1_CII);};
  public CMPAR_DDR_TRAN_RUN_CII MPAR_DDR_TRAN_RUN_CII() {return(_MPAR_DDR_TRAN_RUN_CII);};
  public CCII_ACCESS_LPAR LPAR_DDR_TRAN_STOP_CII() {return(_LPAR_DDR_TRAN_STOP_CII);};
  public CCII_ACCESS_LPAR LPAR_MEM_ACC_CII() {return(_LPAR_MEM_ACC_CII);};
  public CCII_ACCESS_IR BITS_PROC_RUN() {return(_BITS_PROC_RUN);};
  public CCII_ACCESS_RO BITS_PROC_ACTIVE() {return(_BITS_PROC_ACTIVE);};
  public CCII_ACCESS_RO BITS_PROC_ERROR() {return(_BITS_PROC_ERROR);};
  public CCII_ACCESS_RO BITS_DPM_TRAN_READY() {return(_BITS_DPM_TRAN_READY);};
  public CCII_ACCESS_IR BITS_DPM_TRAN_ACK() {return(_BITS_DPM_TRAN_ACK);};
  public CCII_ACCESS_IR BITS_DDR_TRAN_AUTO() {return(_BITS_DDR_TRAN_AUTO);};
  public CCII_ACCESS_IR BITS_DDR_TRAN_SIM() {return(_BITS_DDR_TRAN_SIM);};
  public CCII_ACCESS_IR BITS_DDR_WR0_RD1() {return(_BITS_DDR_WR0_RD1);};
  public CCII_ACCESS_IR BITS_DDR_TRAN_RUN() {return(_BITS_DDR_TRAN_RUN);};
  public CCII_ACCESS_RO BITS_DDR_TRAN_STOP() {return(_BITS_DDR_TRAN_STOP);};
  public CCII_ACCESS_IR WORD_DDR_ADDR() {return(_WORD_DDR_ADDR);};
  public CCII_ACCESS_IR WORD_DDR_MASK() {return(_WORD_DDR_MASK);};
  public CCII_ACCESS_IR WORD_DDR_NUM() {return(_WORD_DDR_NUM);};
  public CCII_DPM COMP_DPM(int num) {return(_COMP_DPM[num].CII_DPM()==null?null:_COMP_DPM[num]);};
}
